Most people probably associate “artificial intelligence” with chatbots. Perhaps some drivers think about “self-driving” features.
However, machine learning and deep neural networks can do so much more, and the prevailing thought makes it seem as if the term “AI” has been hijacked by “GPT.”
Progress in AI has opened up possibilities for new machines that can consistently and reliably perform complex tasks that were previously impossible. However, the more advanced AI becomes, the more power is required to run it.
And if the machine is to be powered by a battery, the chip must be power-efficient.
GlobalFoundries, the fourth-largest outsourced semiconductor manufacturer, completed the acquisition of a chip design company MIPS in August.
In an interview about the acquisition, MIPS CEO Sameer Wasson told TheStreet that MIPS will accelerate its investments by joining a large public company, and that the company should be able to release more products faster and scale its customer engagements.
The results of acceleration are showing.
Image source: MIPS
MIPS I8500 chip unveiled at GlobalFoundries’ Technology Summit
During GlobalFoundries’ Technology Summit in Munich, Germany, on October 15, a new MIPS chip design was unveiled, the I8500, a class of intelligent data movement processor IP intended for real-time, event-driven computing platforms.
Intended for hyperscale, storage, automotive, industrial, and communications infrastructure markets, the I8500 is built to meet the requirements of Physical AI.
Several factors make this chip design particularly interesting. First, it is based on the open source RISC-V instruction set architecture (ISA). Find more information on the benefits of making a chip based on RISC-V here.
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The best way to describe the second reason this MIPS chip design is special is to compare it to a commonly used CPU. For example, one can think of this chip design as a set of Lego pieces that MIPS customers can use to build a chip.
The MIPS I8500 features cores capable of multithreading (4 threads) and up to 6 cores per core cluster (24 threads). As previously explained, by comparing it to Lego, the architecture is scalable, meaning that the system-on-chip built with it can have multiple clusters.
This approach provides MIPS’ customers with incredible flexibility to tweak the final chip to their exact needs.
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Such scalable architecture allows for flexible deployment, and it’s especially suitable for 5G/6G and edge computing environments. The chip features an energy-efficient design, making it ideal for edge AI workloads, along with RVA23 profile readiness and support for Linux and Real-Time operating systems.
The chip is also designed for fast rule-based packet classification, making it convenient for smart network interface controllers, data processing units, and backhaul processors in data centers and telecom networks.
MIPS CEO touts I8500 chip capabilities
Wasson also told TheStreet about the I8500’s performance capabilities:
The I8500 cluster is a building block for data orchestration engines that offload specific tasks from host CPUs. In this role, it is moving data by routing packets as quickly as possible, applying rules for security and priority in a deterministic manner.
The I8500 cluster is a building block for data orchestration engines that offload specific tasks from host CPUs. In this role, it is moving data by routing packets as quickly as possible, applying rules for security and priority in a deterministic manner.
“The metrics for this processor can be seen in the iPerf 3 benchmark (for Ethernet layer 2 forwarding performance) in packets-per-second (pps). We show that on a core basis we can increase pps by 3.5X but keep the same silicon area. This is a crucial measurement in this space, as compute density directly affects product cost and power envelope.”
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Wasson also explained that MIPS has a heritage of multithreading expertise. “While the I8500 is the first MIPS RISC-V processor IP to feature 4 threads, the microarchitecture is our 3rd generation since first introducing the I6400 in 2014.”
Why is this chip so important for pushing physical AI forward? Wasson told TheStreet:
The MIPS I8500 cluster allows a varying mix of 3rd party IP blocks to be directly attached to the coherent cluster, enabling workload-specific AI models or fixed-function accelerators to be closely integrated.
“This deep integration delivers higher levels of efficiency and allows for multi-modal AI or workloads to run across the same data and chip at the same time,” Wasson added. “Through this flexibility of design choice, chip designers can run physical AI models optimized for their use case.”
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